ATmega32A datasheet(81/352 Pages) ATMEL

81 / 352 page

8155B–AVR–07/09

ATmega32A

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct

PWM mode the counter is incremented until the counter value matches MAX. When the counter

reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one

timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 14-7.

The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope

operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal

line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0.

Figure 14-7. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0 pin. Setting the COM01:0 bits to 2 will produce a non-inverted PWM. An inverted PWM out-

put can be generated by setting the COM01:0 to 3 (see Table 14-5 on page 86). The actual OC0

value will only be visible on the port pin if the data direction for the port pin is set as output. The

PWM waveform is generated by clearing (or setting) the OC0 Register at the compare match

between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0

PWM frequency for the output when using phase correct PWM can be calculated by the follow-

ing equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0 Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the out-

TOVn Interrupt Flag Set

OCn Interrupt Flag Set

TCNTn

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

fOCnPCPWM

clk_I/O

N 510

⋅

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