ATmega32A datasheet(82/352 Pages) ATMEL

82 / 352 page

8155B–AVR–07/09

ATmega32A

put will be continuously low and if set equal to MAX the output will be continuously high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 14-7 OCn has a transition from high to low even though

there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-

TOM. There are two cases that give a transition without Compare Match:

• OCR0A changes its value from MAX, like in Figure 14-7. When the OCR0A value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the

way up.

14.8

Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

T0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set. Figure 14-8 contains timing data for basic Timer/Counter operation. The figure

shows the count sequence close to the MAX value in all modes other than phase correct PWM

mode.

Figure 14-8. Timer/Counter Timing Diagram, no Prescaling

Figure 14-9 shows the same timing data, but with the prescaler enabled.

clk

(clk

I/O/1)

TOVn

clk

I/O

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

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