ATmega32A datasheet(20/352 Pages) ATMEL

20 / 352 page

8155B–AVR–07/09

ATmega32A

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This

can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the

internal BOD does not match the needed detection level, an external low V

CC Reset Protec-

tion circuit can be used. If a reset occurs while a write operation is in progress, the write

operation will be completed provided that the power supply voltage is sufficient.

7.5

I/O Memory

The I/O space definition of the ATmega32A is shown in “Register Summary” on page 334.

All ATmega32A I/Os and peripherals are placed in the I/O space. The I/O locations are

accessed by the IN and OUT instructions, transferring data between the 32 general purpose

working registers and the I/O space. I/O Registers within the address range $00 - $1F are

directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single

bits can be checked by using the SBIS and SBIC instructions. Refer to the Instruction Set sec-

tion for more details. When using the I/O specific commands IN and OUT, the I/O addresses $00

- $3F must be used. When addressing I/O Registers as data space using LD and ST instruc-

tions, $20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI

instructions will operate on all bits in the I/O Register, writing a one back into any flag read as

set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

The I/O and Peripherals Control Registers are explained in later sections.

7.6

7.6.1

EEARH and EEARL – EEPROM Address Register

• Bits 15:10 – Res: Reserved Bits

These bits are reserved bits in the ATmega32A and will always read as zero.

• Bits 9:0 – EEAR9:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specify the EEPROM address in the

1024 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and

1023. The initial value of EEAR is undefined. A proper value must be written before the

EEPROM may be accessed.

Bit

151413

121110

–––

EEAR9

EEAR8

EEARH

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

EEARL

765

432

Read/Write

RRR

R/W

Initial Value

XXXX

XXX

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