ATmega32A datasheet(80/352 Pages) ATMEL

80 / 352 page

8155B–AVR–07/09

ATmega32A

inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare

matches between OCR0 and TCNT0.

Figure 14-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Set-

ting the COM01:0 bits to 2 will produce a non-inverted PWM and an inverted PWM output can

be generated by setting the COM01:0 to 3 (See Table 14-4 on page 85). The actual OC0 value

will only be visible on the port pin if the data direction for the port pin is set as output. The PWM

waveform is generated by setting (or clearing) the OC0 Register at the compare match between

OCR0 and TCNT0, and clearing (or setting) the OC0 Register at the timer clock cycle the coun-

ter is cleared (changes from MAX to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0 Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR0 is set equal to BOTTOM, the output will be

a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equal to MAX will result in a

constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.)

14.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM0[1:0] = 1) provides a high resolution phase correct PWM

waveform generation option. The phase correct PWM mode is based on a dual-slope operation.

The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-

inverting Compare Output mode, the Output Compare (OC0) is cleared on the compare match

between TCNT0 and OCR0 while upcounting, and set on the compare match while downcount-

ing. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has

lower maximum operation frequency than single slope operation. However, due to the symmet-

ric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

TCNTn

OCRn Update and

TOVn Interrupt Flag Set

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

fOCnPWM

clk_I/O

N 256

⋅

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