ATmega32A datasheet(12/352 Pages) ATMEL

12 / 352 page

8155B–AVR–07/09

ATmega32A

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

6.5.1

SPH and SPL – Stack Pointer High and Low Register

6.6

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk

CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast-access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 6-4.

The Parallel Instruction Fetches and Instruction Executions

Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Bit

151413121110

SP15

SP14

SP13

SP12

SP11

SP10

SP9

SP8

SPH

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

SPL

543210

Read/Write

R/W

Initial Value

000000

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

CPU

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