ATmega32A datasheet(16/352 Pages) ATMEL

16 / 352 page

8155B–AVR–07/09

ATmega32A

AVR Memories

7.1

Overview

This section describes the different memories in the ATmega32A. The AVR architecture has two

main memory spaces, the Data Memory and the Program Memory space. In addition, the

ATmega32A features an EEPROM Memory for data storage. All three memory spaces are linear

and regular.

7.2

In-System Reprogrammable Flash Program Memory

The ATmega32A contains 32K bytes On-chip In-System Reprogrammable Flash memory for

program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as

16K x 16. For software security, the Flash Program memory space is divided into two sections,

Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega32A

Program Counter (PC) is 14 bits wide, thus addressing the 16K program memory locations. The

operation of Boot Program section and associated Boot Lock bits for software protection are

described in detail in “Boot Loader Support – Read-While-Write Self-Programming” on page

252. “Memory Programming” on page 266 contains a detailed description on Flash Program-

ming in SPI, JTAG, or Parallell Programming mode.

Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory Instruction Description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 12.

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