ATmega32A datasheet(22/352 Pages) ATMEL

22 / 352 page

8155B–AVR–07/09

ATmega32A

Support – Read-While-Write Self-Programming” on page 252 for details about boot

programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is

interrupting another EEPROM Access, the EEAR or EEDR reGister will be modified, causing the

interrupted EEPROM Access to fail. It is recommended to have the Global Interrupt Flag cleared

during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,

the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-

rect address is set up in the EEAR Register, the EERE bit must be written to a logic one to

trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested

data is available immediately. When the EEPROM is read, the CPU is halted for four cycles

before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 7-1 lists the typical pro-

gramming time for EEPROM access from the CPU.

Note:

1. Uses 1 MHz clock, independent of CKSEL Fuse setting.

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (for example by disabling inter-

rupts globally) so that no interrupts will occur during execution of these functions. The examples

also assume that no Flash Boot Loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

Table 7-1.

EEPROM Programming Time

Symbol

Number of Calibrated RC Oscillator

Cycles(1)

Typ Programming Time

EEPROM write (from CPU)

8448

8.5 ms

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