ATmega32A datasheet(102/352 Pages) ATMEL

102 / 352 page

102

8155B–AVR–07/09

ATmega32A

16.7

Compare Match Output Unit

The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses

the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match.

Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 16-5 shows a simplified

schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers

(DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the

OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a System Reset

occur, the OC1x Register is reset to “0”.

Figure 16-5. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform

Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

ble on the pin. The port override function is generally independent of the Waveform Generation

mode, but there are some exceptions. Refer to Table 16-2, Table 16-3 and Table 16-4 for

details.

The design of the output compare pin logic allows initialization of the OC1x state before the out-

put is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of

operation. See “Register Description” on page 112.

The COM1x1:0 bits have no effect on the Input Capture unit.

16.7.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.

For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the

OC1x Register is to be performed on the next compare match. For compare output actions in the

non-PWM modes refer to Table 16-2 on page 112. For fast PWM mode refer to Table 16-3 on

page 113, and for phase correct and phase and frequency correct PWM refer to Table 16-4 on

page 113.

PORT

DDR

OCnx

Waveform

Generator

COMnx1

COMnx0

FOCnx

clk

I/O

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