ATtiny25 datasheet(138/196 Pages) ATMEL

138 / 196 page

138

7598H–AVR–07/09

ATtiny25/45/85

21.6

Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-

put). After RESET is set low, the Programming Enable instruction needs to be executed first

before program/erase operations can be executed. NOTE, in Table 21-8 on page 138, the pin

mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal

SPI interface.

Figure 21-1. Serial Programming and Verify

(1)

Notes:

1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

CLKI pin.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High: > 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

21.6.1

Serial Programming Algorithm

When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK.

When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See

Figure 21-2 and Figure 21-3 for timing details.

Table 21-8.

Pin Mapping Serial Programming

Symbol

Pins

I/O

Description

MOSI

PB0

Serial Data in

MISO

PB1

Serial Data out

SCK

PB2

Serial Clock

VCC

GND

SCK

MISO

MOSI

RESET

+4.5 - 5.5V

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