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ATtiny25 датащи(PDF) 115 Page - ATMEL Corporation |
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ATtiny25 датащи(HTML) 115 Page - ATMEL Corporation |
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115 / 196 page ![]() 115 7598H–AVR–07/09 ATtiny25/45/85 The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously reset when ADEN is low. When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle. A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry. The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver- sion and 14.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new conversion will be initiated on the first rising ADC clock edge. When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi- tional CPU clock cycles are used for synchronization logic. In Free Running mode, a new conversion will be started immediately after the conversion com- pletes, while ADSC remains high. For a summary of conversion times, see Table 18-1. Figure 18-4. ADC Timing Diagram, First Conversion (Single Conversion Mode) Sign and MSB of Result LSB of Result ADC Clock ADSC Sample & Hold ADIF ADCH ADCL Cycle Number ADEN 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 First Conversion Next Conversion 3 MUX and REFS Update MUX and REFS Update Conversion Complete |
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