MCP4728 datasheet(6/66 Pages) MICROCHIP

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MCP4728

DS22187C-page 6

DAC-to-DAC Crosstalk

—

<10

—

nV-s

Digital Interface

Output Low Voltage

VOL

—

0.4

IOL = 3 mA

SDA and RDY/BSY pins

Schmitt Trigger

Low Input

Threshold Voltage

VIL

—

0.3VDD

VDD > 2.7V.

SDA, SCL, LDAC pins

—

0.2VDD

VDD ≤ 2.7V.

SDA, SCL, LDAC pins

Schmitt Trigger

High Input

Threshold Voltage

VIH

0.7VDD

—

SDA, SCL, LDAC pins

Input Leakage

ILI

—

±1

µA

SCL = SDA = LDAC = VDD,

SCL = SDA = LDAC = VSS

Pin Capacitance

CPIN

——

(Note 4)

EEPROM

EEPROM Write Time

TWRITE

—

EEPROM write time

Data Retention

—

200

—

Years

At +25°C,

(Note 3)

LDAC Input

LDAC Low Time

TLDAC

210

—

Updates analog outputs

(Note 3)

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at V

DD = + 2.7V to 5.5V, VSS = 0V,

RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS.

Parameter

Symbol

Min

Typical

Max

Units

Conditions

Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0x000.

2: The power-up ramp rate measures the rise of V

DD over time.

3: This parameter is ensured by design and not 100% tested.

4: This parameter is ensured by characterization and not 100% tested.

5: Test code range: 100 - 4000 codes, V

REF = VDD, VDD = 5.5V.

6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.

7: This parameter is indirectly tested by Offset and Gain error testing.

8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.

9: This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of V

OUT.

This time delay is not included in the output settling time specification.

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