MCP4728 datasheet(5/66 Pages) MICROCHIP

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DS22187C-page 5

MCP4728

Full Scale Range

(Note 7)

FSR

—

VDD

—V

VREF = VDD

FSR = from 0.0V to VDD

—VREF

—V

VREF = Internal, Gx =1,

FSR = from 0.0 V to VREF

—2 * VREF

—V

VREF = Internal, Gx =2,

FSR = from 0.0V to 2*VREF

Output Voltage Settling

Time

TSETTLING

—6

—

µs

(Note 8)

Analog Output Time Delay

from Power-Down Mode

TdExPD

—4.5

—

µs

VDD = 5V, (Note 4), (Note 9)

Time delay to settle to new

reference

(Note 4)

TdREF

—

µs

From External to Internal

Reference

—

µs

From Internal to External

Reference

Power Supply Rejection

PSRR

—

-57

—

VDD = 5V± 10%, VREF = Internal

Capacitive Load Stability

—

1000

RL = 5 kΩ, No Oscillation, (Note 4)

Slew Rate

—

0.55

—

V/µs

Phase Margin

—

Degree

(°)

CL = 400 pF, RL = ∞

Short Circuit Current

ISC

—15

VDD = 5V,

All VOUT Pins = Grounded.

Tested at room temperature.

Short Circuit Current

Duration

TSC_DUR

—

Infinite

—

hours

(Note 4)

DC Output Impedance

(Note 4)

ROUT

—1

—

Normal mode

—1

—

Power-Down Mode 1

(PD1:PD0 = 0:1), VOUT to VSS

—100

—

Power-Down Mode 2

(PD1:PD0 = 1:0), VOUT to VSS

—500

—

Power-Down Mode 3

(PD1:PD0 = 1:1), VOUT to VSS

Dynamic Performance (Note 4)

Major Code Transition

Glitch

—

nV-s

1 LSB code change around major

carry (from 7FFh to 800h)

Digital Feedthrough

—

<10

—

nV-s

Analog Crosstalk

—

<10

—

nV-s

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at V

DD = + 2.7V to 5.5V, VSS = 0V,

RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS.

Parameter

Symbol

Min

Typical

Max

Units

Conditions

Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0x000.

2: The power-up ramp rate measures the rise of V

DD over time.

3: This parameter is ensured by design and not 100% tested.

4: This parameter is ensured by characterization and not 100% tested.

5: Test code range: 100 - 4000 codes, V

REF = VDD, VDD = 5.5V.

6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.

7: This parameter is indirectly tested by Offset and Gain error testing.

8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.

9: This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of V

OUT.

This time delay is not included in the output settling time specification.

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