MCP4728 datasheet(23/66 Pages) MICROCHIP

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DS22187C-page 23

MCP4728

4.0

THEORY OF DEVICE

OPERATION

The MCP4728 device is a 12-bit 4-channel buffered

voltage

output

DAC

with

non-volatile

memory

(EEPROM). The user can program the EEPROM with

I2C address bits, configuration and DAC input data of

each channel. The device has an internal charge pump

circuit to provide the programming voltage of the

EEPROM.

When the device is first powered-up, it automatically

loads the stored data in its EEPROM to the DAC input

and output registers, and provides analog outputs with

the saved settings immediately. This event does not

require an LDAC or UDAC bit condition. After the

device is powered-up, the user can update the input

registers using I2C write commands. The analog out-

puts can be updated with new register values if the

LDAC pin or UDAC bit is low. The DAC output of each

channel is buffered with a low power and precision out-

put amplifier. This amplifier provides a rail-to-rail output

with low offset voltage and low noise.

The device uses a resistor string architecture. The

resistor ladder DAC can be driven from VDD or internal

VREF depending on the reference selection. The user

can select internal (2.048V) or external reference (VDD)

for each DAC channel individually by software control.

The VDD is used as the external reference. Each

channel is controlled and operated independently.

The device has a Power-Down mode feature. Most of

the circuit in each powered down channel are turned

off.

Therefore,

operating

power

can

saved

significantly by putting any unused channel to the

Power-Down mode.

4.1

Power-On-Reset (POR)

The device contains an internal Power-On-Reset

(POR) circuit that monitors power supply voltage (VDD)

during operation. This circuit ensures correct device

start-up at system power-up and power-down events.

If the power supply voltage is less than the POR

threshold (VPOR = 2V, typical), all circuits are disabled

and there will be no analog output. When the VDD

increases above the VPOR, the device takes a reset

state. During the reset period, each channel uploads all

configuration and DAC input codes from EEPROM,

and analog output (VOUT) will be available accordingly.

This enables the device to return to the same state that

it was at the last write to the EEPROM before it was

powered off. The POR status is monitored by the POR

status bit by using the I2C read command. See

Figure 5-15 for the details of the POR status bit.

4.2

Reset Conditions

The device can be reset by two independent events: (a)

by Power-On-Reset or (b) by I2C General Call Reset

Command. Under the reset conditions, the device

uploads the EEPROM data into both of the DAC input

and output registers simultaneously. The analog output

voltage of each channel is available immediately

regardless of the LDAC and UDAC bit conditions.

The factory default settings for the EEPROM prior to

the device shipment are shown in Table 4-2.

4.3

Output Amplifier

The DAC output is buffered with a low power precision

amplifier. This amplifier provides low offset voltage and

low noise, as well as rail-to-rail output.

The output amplifier can drive the resistive and high

capacitive loads without oscillation. The amplifier can

provide a maximum load current of 24 mA which is

enough for most of programmable voltage reference

applications.

Refer

Section 1.0

“Electrical

Characteristics” for the specifications of the output

amplifier.

4.3.1

PROGRAMMABLE GAIN BLOCK

The rail-to-rail output amplifier of each channel has

configurable gain option. When the internal voltage

reference is selected, the output amplifier gain has two

selection options: gain of 1 or gain of 2.

When the external reference is selected (VREF = VDD),

the gain of 2 option is disabled, and only the gain of 1

is used by default.

4.3.1.1

Resistive and Capacitive Loads

The analog output (VOUT) pin is capable of driving

capacitive loads up to 1000 pF in parallel with 5 k

load resistance. Figure 2-42 shows the VOUT vs.

Resistive Load.

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