MCP4728 datasheet(4/66 Pages) MICROCHIP

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MCP4728

DS22187C-page 4

Power-On-Reset

Threshold Voltage

VPOR

—

2.2

—

All circuits including EEPROM are

ready to operate.

Power-Up Ramp Rate

VRAMP

1—

—

V/s

Note 2, Note 4

DC Accuracy

Resolution

—

Bits

Code Change: 000h to FFFh

INL Error

INL

—

±2

±13

LSB

(Note 5)

DNL Error

DNL

-0.75

±0.2

±0.75

LSB

(Note 5)

Offset Error

VOS

—

0.02

0.75

% of

FSR

Code = 000h

Offset Error Drift

ΔV

OS/°C

—

±0.16

—

ppm/°C -45°C to 25°C

—

±0.44

—

ppm/°C +25°C to +125°C

Gain Error

-3

-0.1

% of

FSR

VREF = Internal, Gain = x1

Code = FFFh,

Offset error is not included.

-3

-0.1

% of

FSR

VREF = Internal, Gain = x2

Code = FFFh,

Offset error is not included.

-2

-0.1

% of

FSR

VREF = VDD

Code = FFFh,

Offset error is not included.

Gain Error Drift

ΔG

E/°C

—

-3

—

ppm/°C

Internal Voltage Reference (VREF), (Note 3)

Internal Voltage Reference

VREF

2.007

2.048

2.089

Temperature Coefficient

ΔV

REF/°C

—

125

0.25

—

ppm/°C

LSB/°C

-40 to 0°C

—

0.09

—

ppm/°C

LSB/°C

0 to +125°C

Reference Output Noise

ENREF

—

290

—

µVp-p

Code = FFFh,

0.1 - 10 Hz, Gx=1

Output Noise Density

eNREF

—

1.2

—

Code = FFFh, 1 kHz, Gx=1

—

1.0

—

Code = FFFh, 10 kHz, Gx=1

1/f Corner Frequency

fCORNER

—

400

—

Analog Output (Output Amplifier)

Output Voltage Swing

VOUT

—

FSR

—

(Note 7)

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at V

DD = + 2.7V to 5.5V, VSS = 0V,

RL = 5 kΩ, CL = 100 pF, GX = 1, TA = -40°C to +125°C. Typical values are at +25°C, VIH = VDD, VIL = VSS.

Parameter

Symbol

Min

Typical

Max

Units

Conditions

Note 1: All digital input pins (SDA, SCL, LDAC) are tied to “High”, Output pins are unloaded, code = 0x000.

2: The power-up ramp rate measures the rise of V

DD over time.

3: This parameter is ensured by design and not 100% tested.

4: This parameter is ensured by characterization and not 100% tested.

5: Test code range: 100 - 4000 codes, V

REF = VDD, VDD = 5.5V.

6: Time delay to settle to a new reference when switching from external to internal reference or vice versa.

7: This parameter is indirectly tested by Offset and Gain error testing.

8: Within 1/2 LSB of the final value when code changes from 1/4 of to 3/4 of full scale.

9: This time delay is measured from the falling edge of ACK pulse in I2C command to the beginning of V

OUT.

This time delay is not included in the output settling time specification.

μV

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