TSB41BA3DIPFP datasheet(51/59 Pages) TI

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(a)

(b)

(c)

FF (data-on)

D0–D7

CTL0, CTL1

PCLK

Transmit

TSB41BA3D

www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009

d. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data on

the D lines with receive on the CTL lines for the remainder of the receive operation.

e. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one idle cycle following a receive operation.

Figure 28. Null Packet Reception Timing

The sequence of events for a null packet reception is as follows:

a. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status

transfer operation that is in progress so that the CTL lines can change from status to receive without an

intervening idle.

b. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.

c. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one idle cycle following a receive operation.

Table 38. Receive Speed Codes and Format

D0–D7(1)

DATA RATE AND FORMAT

0000 0000

S100 legacy

0000 0001

S100 Beta

0000 0100

S200 legacy

0000 0101

S200 Beta

0000 1000

S400 legacy

0000 1001

S400 Beta

0000 1101

S800 Beta

1111 1111

Data-on indication

All others

Reserved

(1)

Y = Output as 1 by PHY, ignored by LLC.

X = Output as 0 by PHY, ignored by LLC.

When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If

the PHY wins arbitration for the serial bus, then the PHY-LLC interface bus is granted to the LLC by asserting

the grant state (11b) on the CTL terminals and the grant type on the D terminals for one PCLK cycle, followed by

idle for one clock cycle. The LLC then takes control of the bus by asserting either idle (00b), hold (11b), or

transmit (01b) on the CTL terminals. If the PHY does not detect a hold or transmit state within eight PCLK cycles,

then the PHY takes control of the PHY-link interface. The hold state is used by the LLC to retain control of the

bus while it prepares data for transmission. The LLC can assert hold for zero or more clock cycles (that is, the

LLC need not assert hold before transmit). During the hold state, the LLC is expected to drive the D lines to 0.

The PHY asserts data-prefix on the serial bus during this time.

When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first

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