TSB41BA3DIPFP datasheet(30/59 Pages) TI

30 / 59 page

49.152 MHz

CPHY + CBD

C10

Bus Reset

TSB41BA3D

SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com

Figure 10. Load Capacitance for the TSB41BA3D PHY

NOTE:

The layout of the crystal portion of the PHY circuit is important for obtaining the

correct frequency, minimizing noise introduced into the PHY's phase-locked loop, and

minimizing any emissions from the circuit. The crystal and two load capacitors must

be considered as a unit during layout. The crystal and load capacitors must be placed

as close as possible to one another while minimizing the loop area created by the

combination of the three components. Varying the size of the capacitors can help in

this. Minimizing the loop area minimizes the effect of the resonant current (IS) that

flows in this resonant circuit. This layout unit (crystal and load capacitors) must then

be placed as close as possible to the PHY XI and XO terminals to minimize trace

lengths.

Figure 11. Recommended Crystal and Capacitor Layout

It is strongly recommended that part of the verification process for the design be to measure the frequency of the

PCLK output of the PHY. This should be done using a frequency counter with an accuracy of six digits or better.

If the PCLK frequency is more than the crystal's tolerance from 49.152 MHz or 98.304 MHz, then the load

capacitance of the crystal can be varied to improve frequency accuracy. If the frequency is too high, add more

load capacitance; if the frequency is too low, decrease the load capacitance. Typically, changes must be done to

both load capacitors (C9 and C10 in Figure 11) at the same time, and both must be of the same value. Additional

design details and requirements can be provided by the crystal vendor.

It is recommended, that whenever the user has a choice, the user should initiate a bus reset by writing to the

initiate-short-bus-reset (ISBR) bit (bit 1, PHY register 0101b). Care must be taken to not change the value of any

of the other writeable bits in this register when the ISBR bit is written to.

In the TSB41BA3D, the initiate-bus-reset (IBR) bit can be set to 1 in order to initiate a bus reset and initialization

sequence; however, it is recommended to use the ISBR bit instead. The IBR bit is located in PHY register 1

along with the root-holdoff bit (RHB) and gap-count register. As required by the 1394b Supplement, this

configuration maintains compatibility with older Texas Instruments PHY designs which were based on either the

suggested register set defined in Annex J of IEEE Std 1394-1995 or the 1394a-2000 Supplement. Therefore,

whenever the IBR bit is written, the RHB and gap-count register are also necessarily written.

Submit Documentation Feedback

Product Folder Link(s): TSB41BA3D

TSB41BA3DIPFP датащи(PDF) 30 Page - Texas Instruments

TSB41BA3DIPFP датащи(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

датащи скачать

ссылки URL