TSB41BA3DIPFP datasheet(28/59 Pages) TI

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Power-Up Reset

TSB41BA3D

SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com

The TSB41BA3D also functions with an LLC that is compliant with the older 1394 standards. This interface is

compatible with both the older Annex J interface specified in the IEEE Std 1394-1995 (with the exception of the

Annex J isolation interfacing method) and the PHY-LLC interface specified in 1394a-2000. When using an LLC

that is compliant with the IEEE 1394b-2002 interface, the BMODE input must be tied low.

When the BMODE input is tied low, the TSB41BA3D implements the PHY-LLC interface specified in the

1394a-2000 Supplement. This interface is based on the interface described in informative Annex J of IEEE Std

1394-1995, which is the interface used in the oldest Texas Instruments PHY devices. The PHY-LLC interface

specified in 1394a-2000 is compatible with the older Annex J. However, the TSB41BA3D does not support the

Annex J isolation interfacing method. When implementing the 1394a-2000 interface, certain signals are not used:

• The PINT output (terminal 1) can be left open.

• The LCLK_PMC input (terminal 7) must be tied directly to ground or through a pulldown resistor of ~1 kΩ or

less, unless the PMC mode is desired (see LCLK_PMC terminal description).

All other signals are connected to their counterparts on the 1394a link-layer controller. The PCLK output

corresponds to the SCLK input signal on most LLCs.

The 1394a-2000 Supplement includes enhancements to the Annex J interface that should be comprehended

when using the TSB41BA3D with a 1394-1995 LLC device.

• A new LLC service request was added which allows the LLC to temporarily enable and disable asynchronous

arbitration accelerations. If the LLC does not implement this new service request, then the arbitration

enhancements must not be enabled (see the EAA bit in PHY register 5).

• The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was

added in order to improve bus efficiency (primarily during isochronous transmission). If the LLC does not

support multispeed concatenation, then multispeed concatenation must not be enabled in the PHY (see the

EMC bit in PHY register 5).

• In order to accommodate the higher transmission speeds expected in future revisions of the standard,

1394a-2000 extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus

request from 7 bits to 8 bits. The new speed codes were carefully selected so that new 1394a-2000 PHY and

LLC devices would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use

the 2-bit speed codes. The TSB41BA3D correctly interprets both 7-bit bus requests (with 2-bit speed code)

and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately followed by

another request (for example, a register read or write request), then the TSB41BA3D correctly interprets both

requests. Although the TSB41BA3D correctly interprets 8-bit bus requests, a request with a speed code

exceeding S400 while in 1394a-2000 PHY-link interface mode results in the TSB41BA3D transmitting a null

packet (data prefix followed by data end, with no data in the packet).

To ensure proper operation of the TSB41BA3D, the RESET terminal must be asserted low for a minimum of

2 ms from the time that PHY power reaches the minimum required supply voltage and the input clock to the PHY

is valid. When using a passive capacitor on the RESET terminal to generate a power-on-reset signal, the

minimum reset time is ensured if the value of the capacitor satisfies the following equation (the value must be no

smaller than approximately 0.1

µF):

Cmin = 0.0077 × T + 0.085 + (external_oscillator_start-up_time × 0.05)

Where Cmin is the minimum capacitance on the RESET terminal in µF, T is the VDD ramp time, 10%–90%, in ms,

external_oscillator_start-up_time is the time in ms from application of power to the external oscillator until the

oscillator

outputs

valid

clock.

crystal

used

rather

than

oscillator,

then

the

external_oscillator_start-up_time can be set to 0.

For example with a 2-ms power ramp time and a 2-ms oscillator start-up time:

Cmin = 0.0077 × 2 + 0.085 + (2 × 0.05) = 0.2 µF

It is appropriate to select the nearest standard value capacitor that exceeds this value, for example 0.22

µF.

Or with a 2-ms power ramp time and a 49.152-MHz fundamental crystal:

Cmin = 0.0077 × 2 + 0.085 + (0 × 0.05) = 0.1 µF

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