TSB41BA3DIPFP datasheet(41/59 Pages) TI

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PCLK

(a)

(c)

(b)

CTL0, CTL1

D0–D7

LREQ

LPS

(d)

tLPS_RESET

tRESTORE

TSB41BA3D

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Table 24. LPS Timing Parameters

SYMBOL

DESCRIPTION

MIN

MAX

UNIT

tLPSL

LPS low time (when pulsed)(1)

0.09

2.6

µs

tLPSH

LPS high time (when pulsed)(1)

0.021

2.6

µs

tLPS_DUTY

LPS duty cycle (when pulsed)(2)

20%

60%

tLPS_RESET

Time for PHY to recognize LPS deasserted and reset the interface

2.6

2.68

µs

tLPS_DISABLE

Time for PHY to recognize LPS deasserted and disable the interface

26.03

26.11

µs

tRESTORE

Time to permit optional isolation circuits to restore during an interface reset

23(3)

µs

PHY not in low-power state

tCLK_ACTIVATE

Time for PCLK to be activated from reassertion of LPS

PHY in low-power state

5.3

7.3

(1)

The specified tLPSL and tLPSH times are worst-case values appropriate for operation with the TSB41BA3D. These values are broader

than those specified for the same parameters in the 1394a-2000 Supplement (that is, an implementation of LPS that meets the

requirements of 1394a-2000 operates correctly with the TSB41BA3D).

(2)

A pulsed LPS signal must have a duty cycle (ratio of tLPSH to cycle period) in the specified range to ensure proper operation when using

an isolation barrier on the LPS signal (for example, as shown in Figure 8).

(3)

The maximum value for tRESTORE does not apply when the PHY-LLC interface is disabled, in which case an indefinite time can elapse

before LPS is reasserted. Otherwise, in order to reset but not disable the interface, it is necessary that the LLC ensure that LPS is

deasserted for less than tLPS_DISABLE.

The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request

activity. When the PHY observes that LPS has been deasserted for tLPS_RESET, it resets the interface. When the

interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity on

the LREQ signal. Figure 19 shows the timing for interface reset.

Figure 19. Interface Reset

The sequence of events for resetting the PHY-LLC interface is as follows:

a. Normal operation. Interface is operating normally, with LPS asserted, PCLK active, status and packet data

reception and transmission via the CTL and D lines, and request activity via the LREQ line. In Figure 19, the

LPS signal is shown as a nonpulsed level signal. However, it is permissible to use a pulsed signal for LPS in

a direct connection between the PHY and LLC; a pulsed signal is required when using an isolation barrier.

b. LPS deasserted. The LLC deasserts the LPS signal and, within 1

µs, terminates any request or interface bus

activity, places its CTL and D outputs into the high-impedance state, and drives its LREQ output low.

c. Interface reset. After tLPS_RESET time, the PHY determines that LPS is inactive, terminates any interface bus

activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.

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