TSB41BA3DIPFP datasheet(38/59 Pages) TI

38 / 59 page

(a)

(b)

(c)

FF (data-on)

D0–D7

CTL0, CTL1

SYSCLK

Transmit

TSB41BA3D

SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com

The PHY asserts at least one idle cycle following a receive operation.

Figure 16. Null Packet Reception Timing

The sequence of events for a null packet reception is as follows:

a. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.

Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status

transfer operation that is in progress so that the CTL lines can change from status to receive without an

intervening idle.

b. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.

c. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.

The PHY asserts at least one idle cycle following a receive operation.

Table 23. Receive Speed Codes

D0–D7(1)

DATA RATE

00XX XXXX

S100

0100 XXXX

S200

0101 0000

S400

11YY YYYY

data-on indication

(1)

X = Output as 0 by PHY, ignored by LLC.

Y = Output as 1 by PHY, ignored by LLC.

When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If

the PHY wins arbitration for the serial bus, then the PHY-LLC interface bus is granted to the LLC by asserting

the grant state (11b) on the CTL terminals for one PCLK cycle, followed by idle for one clock cycle. The LLC then

takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless

the LLC is immediately releasing the interface, the LLC can assert the idle state for at most one clock before it

must assert either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain control of

the bus while it prepares data for transmission. The LLC can assert hold for zero or more clock cycles (that is,

the LLC need not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this time.

Submit Documentation Feedback

Product Folder Link(s): TSB41BA3D

TSB41BA3DIPFP датащи(PDF) 38 Page - Texas Instruments

TSB41BA3DIPFP датащи(HTML) 38 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59

датащи скачать

ссылки URL