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TSB41BA3DIPFP датащи(PDF) 45 Page - Texas Instruments |
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TSB41BA3DIPFP датащи(HTML) 45 Page - Texas Instruments |
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45 / 59 page ![]() LLC Service Request Each cell represents one clock sample period, and n is the number of bits in the request stream. LR1 LR2 LR3 LR (n-2) LR0 LR (n-1) TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. Table 25 and Table 26 show the encoding of the CTL0–CTL1 bus. Table 25. CTL Encoding When PHY Has Control of the Bus CTL0 CTL1 NAME DESCRIPTION 0 0 Idle No activity (this is the default mode) 0 1 Status Status information is being sent from the PHY to the LLC. 1 0 Receive An incoming packet is being sent from the PHY to the LLC. 1 1 Grant The LLC has been given control of the bus to send an outgoing packet. Table 26. CTL Encoding When LLC Has Control of the Bus CTL0 CTL1 NAME DESCRIPTION 0 0 Idle The LLC releases the bus (transmission has been completed). 0 1 Transmit An outgoing packet is being sent from the LLC to the PHY. 1 0 Reserved Reserved 1 1 Holation The LLC is holding the bus while data is being prepared for transmission, or the LLC is sending a request to arbitrate for access to the bus, or the LLC is identifying the end of a subaction gap to the PHY. To request access to the bus, to read or write a PHY register, or to send a link notification to PHY, the LLC sends a serial bit stream on the LREQ terminal as shown in Figure 23. Figure 23. LREQ Request Stream The length of the stream varies depending on the type of request as shown in Table 27. Table 27. Request Stream Bit Length REQUEST TYPE NUMBER OF BITS Bus request 11 Read register request 10 Write register request 18 Link notification request 6 PHY-link interface reset request 6 Regardless of the type of request, a start bit of 1 is required at the beginning of the stream and a stop bit of 0 is required at the end of the stream. The second through fifth bits of the request stream indicate the type of the request. In the following descriptions, bit LR1 is the most significant and is transmitted first in the request bit stream. The LREQ terminal is normally low. Copyright © 2008–2009, Texas Instruments Incorporated Submit Documentation Feedback 45 Product Folder Link(s): TSB41BA3D |
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