4513 datasheet(116/210 Pages) RENESAS

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APPLICATION

2.2 Interrupts

2-13

4513/4514 Group User’s Manual

(7)

A-D interrupt

The interrupt request occurs by the end of the A-D conversion.

s A-D interrupt processing

q When the interrupt is used

The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the

interrupt enable flag INTE are set to “1.” When the A-D interrupt occurs, the interrupt processing

is executed from address C in page 1.

q When the interrupt is not used

The interrupt is disabled and the SNZAD instruction is valid when the bit 2 of register V2 is set

to “0.”

(8)

Serial I/O interrupt

The interrupt request occurs by the end of the serial I/O transmit/receive.

s Serial I/O interrupt processing

q When the interrupt is used

The interrupt occurrence is enabled when the bit 3 of the interrupt control register V2 and the

interrupt enable flag INTE are set to “1.” When the serial I/O interrupt occurs, the interrupt

processing is executed from address E in page 1.

q When the interrupt is not used

The interrupt is disabled and the SNZSI instruction is valid when the bit 3 of register V2 is set

to “0.”

2.2.2 Related registers

(1)

Interrupt enable flag (INTE)

The interrupt enable flag (INTE) controls whether the every interrupt enable/disable.

Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE

flag is cleared to “0” with the DI instruction.

When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are

disabled until the EI instruction is executed.

Note: The interrupt enabled with the EI instruction is performed after the EI instruction and one more

instruction.

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