4513 datasheet(63/210 Pages) RENESAS

63 / 210 page

1-50

HARDWARE

4513/4514 Group User’s Manual

FUNCTION BLOCK OPERATIONS

(1) Power-on reset

Reset can be performed automatically at power on (power-on re-

set) by connecting resistors, a diode, and a capacitor to RESET

pin. Connect RESET pin and the external circuit at the shortest dis-

tance.

Fig. 34 Power-on reset circuit example

(2) Internal state at reset

Table 19 shows port state at reset, and Figure 35 shows inter nal

state at reset (they are the same after system is released from re-

set). The contents of timers, registers, flags and RAM except

shown in Figure 35 are undefined, so set the initial value to them.

Table 19 Port state at reset

Name

D0–D5

D6/CNTR0, D7/CNTR1

P00–P03

P10–P13

P20/SCK, P21/SOUT, P22/SIN

P30/INT0, P31/INT1

P32, P33 (Note 4)

P40/AIN4–P43/AIN7 (Note 4)

P50–P53 (Note 4)

Notes 1: Output latch is set to “1.”

2: Pull-up transistor is turned OFF.

3: After system is released from reset, port P5 is in the input mode. (Direction register FR0 = 00002)

4: The 4513 Group does not have these ports.

Function

D0–D5

D6, D7

P00–P03

P10–P13

P20–P22

P30, P31

P32, P33

P40–P43

P50–P53

State

High impedance (Note)

High impedance (Notes 1, 2)

High impedance

High impedance (Note 1)

High impedance (Note 3)

VDD

RESET pin

WEF

(Note)

Internal reset signal

Voltage drop detection circuit

Watchdog timer output

VDD

RESET pin voltage

Power-on

Reset released

Internal reset signal

Reset state

Note:

This symbol represents a parasitic diode.

Applied potential to RESET pin must be VDD or less.

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