4513 datasheet(10/210 Pages) RENESAS

10 / 210 page

4513/4514 Group User’s Manual

List of figures

Fig. 42 Ceramic resonator external circuit ............................................................................... 1-58

Fig. 43 External clock input circuit ............................................................................................ 1-58

Fig. 44 External 0 interrupt program example ......................................................................... 1-59

Fig. 45 External 1 interrupt program example ......................................................................... 1-59

Fig. 46 A-D converter operating mode program example ...................................................... 1-60

Fig. 47 Analog input external circuit example-1 ...................................................................... 1-60

Fig. 48 Analog input external circuit example-2 ...................................................................... 1-60

Fig. 49 Pin configuration of built-in PROM version of 4513 Group...................................... 1-88

Fig. 50 Pin configuration of built-in PROM version of 4514 Group...................................... 1-88

Fig. 51 PROM memory map ....................................................................................................... 1-89

Fig. 52 Flow of writing and test of the product shipped in blank......................................... 1-89

CHAPTER 2 APPLICATION

Fig. 2.1.1 Key input by key scan................................................................................................. 2-7

Fig. 2.1.2 Key scan input timing .................................................................................................. 2-8

Fig. 2.2.1 INT0 interrupt operation example ............................................................................ 2-17

Fig. 2.2.2 INT0 interrupt setting example ................................................................................. 2-18

Fig. 2.2.3 INT1 interrupt operation example ............................................................................ 2-19

Fig. 2.2.4 INT1 interrupt setting example ................................................................................. 2-20

Fig. 2.2.5 Timer 1 constant period interrupt setting example................................................ 2-21

Fig. 2.2.6 Timer 2 constant period interrupt setting example................................................ 2-22

Fig. 2.2.7 Timer 3 constant period interrupt setting example................................................ 2-23

Fig. 2.2.8 Timer 4 constant period interrupt setting example................................................ 2-24

Fig. 2.3.1 Peripheral circuit example ......................................................................................... 2-30

Fig. 2.3.2 Watchdog timer function............................................................................................ 2-31

Fig. 2.3.3 Constant period measurement setting example ..................................................... 2-32

Fig. 2.3.4 CNTR0 output setting example ................................................................................ 2-33

Fig. 2.3.5 CNTR1 input setting example .................................................................................. 2-34

Fig. 2.3.6 CNTR0 output control setting example ................................................................... 2-35

Fig. 2.3.7 Timer start by external input setting example (1) ................................................. 2-36

Fig. 2.3.8 Timer start by external input setting example (2) ................................................. 2-37

Fig. 2.3.9 Watchdog timer setting example .............................................................................. 2-38

Fig. 2.4.1 Serial I/O block diagram ........................................................................................... 2-40

Fig. 2.4.2 Serial I/O connection example ................................................................................. 2-42

Fig. 2.4.3 Serial I/O register state when transmitting/receiving ............................................ 2-42

Fig. 2.4.4 Serial I/O transfer timing ........................................................................................... 2-43

Fig. 2.4.5 Master serial I/O setting example ............................................................................ 2-46

Fig. 2.4.6 Slave serial I/O example ........................................................................................... 2-47

Fig. 2.4.7 Input waveform of external clock ............................................................................. 2-48

Fig. 2.5.1 A-D converter structure ............................................................................................. 2-49

Fig. 2.5.2 A-D conversion mode setting example ................................................................... 2-51

Fig. 2.5.3 Analog input external circuit example-1 .................................................................. 2-52

Fig. 2.5.4 Analog input external circuit example-2 .................................................................. 2-52

Fig. 2.5.5 A-D converter operating mode program example.................................................. 2-52

Fig. 2.7.1 Power-on reset circuit example ................................................................................ 2-56

Fig. 2.7.2 Oscillation stabilizing time after system is released from reset .......................... 2-56

Fig. 2.7.3 Internal state at reset ................................................................................................ 2-57

Fig. 2.8.1 Voltage drop detection reset circuit ......................................................................... 2-58

Fig. 2.8.2 Voltage drop detection circuit operation waveform ............................................... 2-58

Fig. 2.9.1 Start condition identified example ............................................................................ 2-60

Fig. 2.10.1 Oscillation circuit example connecting ceramic resonator externally................ 2-63

Fig. 2.10.2 Structure of clock control circuit ............................................................................ 2-64

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