4513 datasheet(9/210 Pages) RENESAS

9 / 210 page

4513/4514 Group User’s Manual

List of figures

CHAPTER 1 HARDWARE

PIN CONFIGURATION (TOP VIEW) 4513 Group ..................................................................... 1-4

PIN CONFIGURATION (TOP VIEW) 4514 Group ..................................................................... 1-5

BLOCK DIAGRAM (4513 Group) ................................................................................................. 1-6

BLOCK DIAGRAM (4514 Group) ................................................................................................. 1-7

PORT BLOCK DIAGRAMS ......................................................................................................... 1-12

External interrupt circuit structure .............................................................................................. 1-16

Fig. 1 AMC instruction execution example ............................................................................... 1-17

Fig. 2 RAR instruction execution example ............................................................................... 1-17

Fig. 3 Registers A, B and register E ........................................................................................ 1-17

Fig. 4 TABP p instruction execution example .......................................................................... 1-17

Fig. 5 Stack registers (SKs) structure ....................................................................................... 1-18

Fig. 6 Example of operation at subroutine call ....................................................................... 1-18

Fig. 7 Program counter (PC) structure ..................................................................................... 1-19

Fig. 8 Data pointer (DP) structure ............................................................................................. 1-19

Fig. 9 SD instruction execution example .................................................................................. 1-19

Fig. 10 ROM map of M34514M8/E8 ......................................................................................... 1-20

Fig. 11 Page 1 (addresses 008016 to 00FF16) structure ....................................................... 1-20

Fig. 12 RAM map ......................................................................................................................... 1-21

Fig. 13 Program example of interrupt processing ................................................................... 1-23

Fig. 14 Internal state when interrupt occurs ............................................................................ 1-23

Fig. 15 Interrupt system diagram ............................................................................................... 1-23

Fig. 16 Interrupt sequence .......................................................................................................... 1-25

Fig. 17 External interrupt circuit structure ................................................................................ 1-26

Fig. 18 Auto-reload function ....................................................................................................... 1-29

Fig. 19 Timers structure .............................................................................................................. 1-31

Fig. 20 Watchdog timer function ................................................................................................ 1-35

Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer .... 1-35

Fig. 22 Serial I/O structure ......................................................................................................... 1-36

Fig. 23 Serial I/O register state when transferring.................................................................. 1-37

Fig. 24 Serial I/O connection example...................................................................................... 1-38

Fig. 25 Timing of serial I/O data transfer ................................................................................. 1-39

Fig. 26 A-D conversion circuit structure ................................................................................... 1-41

Fig. 27 A-D conversion timing chart .......................................................................................... 1-44

Fig. 28 Setting registers .............................................................................................................. 1-44

Fig. 29 Comparator operation timing chart............................................................................... 1-45

Fig. 30 Definition of A-D conversion accuracy ........................................................................ 1-46

Fig. 31 Voltage comparator structure ........................................................................................ 1-47

Fig. 32 Reset release timing ...................................................................................................... 1-49

Fig. 33 RESET pin input waveform and reset operation ....................................................... 1-49

Fig. 34 Power-on reset circuit example .................................................................................... 1-50

Fig. 35 Internal state at reset .................................................................................................... 1-51

Fig. 36 Voltage drop detection reset circuit ............................................................................. 1-52

Fig. 37 Voltage drop detection circuit operation waveform.................................................... 1-52

Fig. 38 State transition ................................................................................................................ 1-55

Fig. 39 Set source and clear source of the P flag ................................................................. 1-55

Fig. 40 Start condition identified example using the SNZP instruction ................................ 1-55

Fig. 41 Clock control circuit structure ....................................................................................... 1-57

List of figures

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