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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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4513 датащи(PDF) 44 Page - Renesas Technology Corp |
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4513 датащи(HTML) 44 Page - Renesas Technology Corp |
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44 / 210 page  4513/4514 Group User’s Manual HARDWARE 1-31 FUNCTION BLOCK OPERATIONS Fig. 19 Timers structure T4F T3F 10 01 00 W31,W30 0 1 W33(Note 3) 0 1 W43(Note 3) 11 T1F (T2AB) T2F (TAB2) 0 1 W23(Note 3) 0 1 (Note 3) W11 (TR1AB) T1AB T1AB (TAB1) (T4AB) (TAB4) (TR3AB) T3AB T3AB (TAB3) Q R S 1 - - - - - - - - - - - 15 16 WDF1 WDF2 WEF 10 01 00 W21,W20 11 10 01 00 W41,W40 11 Timer 4 interrupt Timer 3 interrupt Not available WRST instruction Timer 2 underflow signal Timer 1 (8) Timer 1 interrupt Reload register R1 (8) Register B Register A Timer 1 underflow signal Timer 2 (8) Reload register R2 (8) Register B Register A Timer 3 (8) Reload register R3 (8) Register B Register A Timer 3 underflow signal Timer 4 (8) Reload register R4 (8) Register B Register A Instruction clock 16-bit timer (WDT) System reset Reset signal Timer 2 interrupt Data is set automatically from each reload register when timer 1, 2, 3, or 4 underflows (auto-reload function) Notes 1: Timer 1 count start synchronous circuit is set by the valid edge of P30/INT0 pin selected by bits 1 (I11) and 2 (I12) of register I1. 2: Timer 3 count start synchronous circuit is set by the valid edge of P31/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2. 3: Count source is stopped by clearing to “0.” Not available Not available Not available Not available ORCLK Q R S W10 1 0 I10 0 1 I11 P30/INT0 1/4 1/16 1 0 W12 1 0 W13 MR3 1 0 XIN Divistion circuit (divided by 2) Instruction clock Internal clock generating circuit (divided by 3) Prescaler 0 1 I12 One-sided edge detection circuit Both edges detection circuit Q R S W32 1 0 I20 0 1 I21 P31/INT1 0 1 I22 One-sided edge detection circuit Both edges detection circuit (Note 1) (Note 2) Falling Rising Falling Rising |
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