4513 datasheet(115/210 Pages) RENESAS

115 / 210 page

APPLICATION

2.2 Interrupts

2-12

4513/4514 Group User’s Manual

(4)

Timer 2 interrupt

The interrupt request occurs by the timer 2 underflow.

s Timer 2 interrupt processing

q When the interrupt is used

The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the

interrupt enable flag INTE are set to “1.” When the timer 2 interrupt occurs, the interrupt processing

is executed from address 6 in page 1.

q When the interrupt is not used

The interrupt is disabled and the SNZT2 instruction is valid when the bit 3 of register V1 is set

to “0.”

(5)

Timer 3 interrupt

The interrupt request occurs by the timer 3 underflow.

s Timer 3 interrupt processing

q When the interrupt is used

The interrupt occurrence is enabled when the bit 0 of the interrupt control register V2 and the

interrupt enable flag INTE are set to “1.” When the timer 3 interrupt occurs, the interrupt processing

is executed from address 8 in page 1.

q When the interrupt is not used

The interrupt is disabled and the SNZT3 instruction is valid when the bit 0 of register V2 is set

to “0.”

(6)

Timer 4 interrupt

The interrupt request occurs by the timer 4 underflow.

s Timer 4 interrupt processing

q When the interrupt is used

The interrupt occurrence is enabled when the bit 1 of the interrupt control register V2 and the

interrupt enable flag INTE are set to “1.” When the timer 4 interrupt occurs, the interrupt processing

is executed from address A in page 1.

q When the interrupt is not used

The interrupt is disabled and the SNZT4 instruction is valid when the bit 1 of register V2 is set

to “0.”

4513 датащи(PDF) 115 Page - Renesas Technology Corp