4513 datasheet(24/210 Pages) RENESAS

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4513/4514 Group User’s Manual

HARDWARE

1-11

Notes 1: The 4513 Group does not have P32 and P33.

2: The 4513 Group does not have these ports.

DEFINITION OF CLOCK AND CYCLE

q System clock

The system clock is the basic clock for controlling this product.

The system clock is selected by the bit 3 of the clock control reg-

ister MR.

PORT FUNCTION

Port

Port D

Port P0

Port P1

Port P2

Port P3

(Note 1)

Port P4

(Note 2)

Port P5

(Note 2)

I/O

unit

Control

instructions

SD, RD

SZD

CLD

OP0A

IAP0

OP1A

IAP1

IAP2

OP3A

IAP3

OP4A

IAP4

OP5A

IAP5

Control

registers

PU0, K0

I1, I2

FR0

Output structure

N-channel open-drain

CMOS

Input

Output

I/O

(8)

I/O

(4)

I/O

(4)

Input

(3)

I/O

(4)

I/O

(4)

I/O

(4)

Remark

Built-in programmable pull-up

functions

Key-on wakeup functions

(programmable)

Built-in programmable pull-up

functions

Key-on wakeup functions

(programmable)

Built-in key-on wakeup

function

(P30/INT0, P31/INT1)

D0–D5

D6/CNTR0

D7/CNTR1

P00–P03

P10–P13

P20/SCK

P21/SOUT

P22/SIN

P30/INT0

P31/INT1

P32, P33

P40/AIN4

–P43/AIN7

P50–P53

MR3

System clock

f(XIN)

f(XIN)/2

Note: f(XIN)/2 is selected after system is released from reset.

q Instruction clock

The instruction clock is a signal derived by dividing the system

clock by 3. The one instruction clock cycle generates the one

machine cycle.

q Machine cycle

The machine cycle is the standard cycle required to execute the

instruction.

Table Selection of system clock

PIN DESCRIPTION

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