7721 datasheet(108/577 Pages) RENESAS

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7721 Group User’s Manual

7–11

INTERRUPTS

The following explains the operation of the interrupt priority detection circuit using Figure 7.5.2.

The interrupt priority level of a requested interrupt (Y in Figure 7.5.2) is compared with the resultant priority

level which is sent from the preceding comparator (X in Figure 7.5.2); the interrupt with the higher priority

level is sent to the next comparator (Z in Figure 7.5.2). (Initial comparison value of “X” is “0.”) For an

interrupt which is not requested, the comparison is not performed and the priority level which is sent from

the preceding comparator is forwarded to the next comparator as it is. When the two priority levels are found

the same by comparison, the priority level which is sent from the preceding comparator is forwarded to the

next comparator. Accordingly, when the same priority level is set by software, the interrupt priority levels are

handled as follows:

DMA3 > DMA2 > DMA1 > DMA0 > A-D conversion > UART1 transmit > UART1 receive > UART0 transmit

> UART0 receive > Timer B2 > Timer B1 > Timer B0 > Timer A4 > Timer A3 > Timer A2 > Timer A1 > Timer

____

A0 > INT2 > INT1 > INT0

Among the multiple interrupt requests sampled at the same time, one request with the highest priority level

is detected by the above comparison.

Then, this highest interrupt priority level is compared with the processor interrupt priority level (IPL). When

this interrupt priority level is higher than the processor interrupt priority level (IPL) and the interrupt disable

flag (I) is “0,” the interrupt request is accepted. A interrupt request which is not accepted here is held until

it is accepted or its interrupt request bit is cleared to “0” by software.

The interrupt priority is detected when the CPU fetches an op code, which is called the CPU’s op-code fetch

cycle. However, when an op-code fetch cycle starts during detection of an interrupt priority, a new interrupt

priority detection does not start. (Refer to “Figure 7.6.1.”) Since the state of the interrupt request bit and

interrupt priority levels are latched during the interrupt priority detection, even if they change, the interrupt

priority detection is performed for the previous state before the change occurred.

The interrupt priority level is detected when the CPU fetches an op code. Therefore, in the following

execution or states, after the execution or state is terminated, no interrupt request is accepted until the CPU

fetches the op code of the next instruction.

•Execution of an instruction which requires many cycles, such as the MVN or MVP instruction

•During DRAM refreshment

•During Hold state

•During DMA transfer

7.5 Interrupt priority level detection circuit

Comparator

(Priority level

comparison)

qWhen X

Y then Z = X

qWhen X

Y then Z = Y

Interrupt source Y

X : Priority level sent from the preceding

comparator (Highest priority at this point)

Y : Priority level of interrupt source Y

Z : Highest priority at this point

Time

Fig. 7.5.2 Interrupt priority level detection model

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