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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HD6432351 датащи(PDF) 171 Page - Renesas Technology Corp |
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HD6432351 датащи(HTML) 171 Page - Renesas Technology Corp |
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171 / 1025 page  Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 137 of 988 REJ09B0330-0300 Bit 5 RCDM Description 0 DRAM interface: RAS up mode selected (Initial value) 1 DRAM interface: RAS down mode selected Bit 4—2-CAS Method Select (CW2): Write 1 to this bit when areas 2 to 5 are designated as 8-bit DRAM space, and 0 otherwise. Bit 4 CW2 Description 0 16-bit DRAM space selected (Initial value) 1 8-bit DRAM space selected Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of the row address in row address/column address multiplexing for the DRAM interface. In burst operation on the DRAM interface, these bits also select the row address to be used for comparison. Bit 3 MXC1 Bit 2 MXC0 Description 0 0 8-bit shift (Initial value) • When 8-bit access space is designated: Row address A23 to A8 used for comparison • When 16-bit access space is designated: Row address A23 to A9 used for comparison 1 9-bit shift • When 8-bit access space is designated: Row address A23 to A9 used for comparison • When 16-bit access space is designated: Row address A23 to A10 used for comparison 1 0 10-bit shift • When 8-bit access space is designated: Row address A23 to A10 used for comparison • When 16-bit access space is designated: Row address A23 to A11 used for comparison 1 — |
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