HD6432351 datasheet(15/1025 Pages) RENESAS

15 / 1025 page

Rev. 3.00 Sep 15, 2006 page xv of xxxiv

Item

Page

Revision (See Manual for Details)

B.1 Addresses

812

Table amended

Address

(low)

Name

H'FF70

PAPCR*

H'FF71

PBPCR*

H'FF72

PCPCR*

H'FF73

PDPCR*

H'FF74

PEPCR*

H'FF76

P3ODR*

H'FF77

PAODR*

813

Table amended

Address

(low)

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

H'FF98

ADCSR

ADF

ADIE

ADST

SCAN

CKS

CH2

CH1

CH0

B.2 Functions

821

Figure amended

TIOR3L H'FE83 TPU3

TGR3D I/O Control

Notes:

Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register.

TGR3D

is output

compare

Output disabled

0 output at compare match

1 output at compare match

Toggle output at compare match

Initial output is 0

output

Output disabled

0 output at compare match

1 output at compare match

Toggle output at compare match

Initial output is 1

output

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Capture input

source is

TIOCD3 pin

TGR3D

is input

capture

Capture input

source is channel

4/count clock

Input capture at TCNT4 count-up/

count-down*1

1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and

φ/1 is used as the TCNT4 count clock,

this setting is invalid and input capture is not generated.

2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid

and input capture/output compare is not generated.

Legend: *: Don’t care

842

Figure amended

ABWCR H'FED0 Bus Controller

ABW7

R/W

Bit

Modes 1 to 3, 5 to 7

Initial value

R/W

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