HD6432351 datasheet(168/1025 Pages) RENESAS

168 / 1025 page

Section 6 Bus Controller

Rev. 3.00 Sep 15, 2006 page 134 of 988

REJ09B0330-0300

6.2.5

Bus Control Register L (BCRL)

BRLE

R/W

BREQOE

R/W

—

R/W

LCASS

R/W

DDS

R/W

WAITE

R/W

—

R/W

WDBE

R/W

Bit

Initial value

R/W

BCRL is an 8-bit readable/writable register that performs selection of the external bus-released

state protocol, the LCAS signal, DMAC single address transfer, enabling or disabling of the write

data buffer function, and enabling or disabling of

WAIT pin input.

BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not

initialized by a manual reset or in software standby mode.

Bit 7—Bus Release Enable (BRLE): Enables or disables external bus release.

Bit 7

BRLE

Description

External bus release is disabled.

BREQ, BACK, and BREQO can be used as I/O ports.

(Initial value)

External bus release is enabled.

Bit 6—BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master

to drop the bus request signal (

BREQ) in the external bus release state, when an internal bus

master performs an external space access, or when a refresh request is generated.

Bit 6

BREQOE

Description

BREQO output disabled. BREQO can be used as I/O port.

(Initial value)

BREQO output enabled.

Bit 5—Reserved: Only 1 should be written to this bit.

Bit 4—LCAS Select (LCASS): Write 0 to this bit when using the DRAM interface.

LCAS pin used for 2-CAS type DRAM interface LCAS signal. BREQO output and WAIT input

cannot be used when

LCAS signal is used.

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