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HD6432351 датащи(PDF) 167 Page - Renesas Technology Corp |
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HD6432351 датащи(HTML) 167 Page - Renesas Technology Corp |
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167 / 1025 page ![]() Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 133 of 988 REJ09B0330-0300 Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description 0 Burst cycle comprises 1 state 1 Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access (Initial value) 1 Max. 8 words in burst access Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced mode. When DRAM space is selected, the relevant area is designated as DRAM interface. Bit 2 RMTS2 Bit 1 RMTS1 Bit 0 RMTS0 Description Area 5 Area 4 Area 3 Area 2 0 Normal space 0 1 Normal space DRAM space 0 Normal space DRAM space 0 1 1 DRAM space 1 — — — Note: When areas selected in DRAM space are all 8-bit space, the PF2 pin can be used as an I/O port, BREQO, or WAIT. |
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