HD6432351 datasheet(22/1025 Pages) RENESAS

22 / 1025 page

Rev. 3.00 Sep 15, 2006 page xxii of xxxiv

6.2.1

Bus Width Control Register (ABWCR)............................................................... 126

6.2.2

Access State Control Register (ASTCR).............................................................. 127

6.2.3

Wait Control Registers H and L (WCRH, WCRL) .............................................. 128

6.2.4

Bus Control Register H (BCRH).......................................................................... 132

6.2.5

Bus Control Register L (BCRL)........................................................................... 134

6.2.6

Memory Control Register (MCR) ........................................................................ 136

6.2.7

DRAM Control Register (DRAMCR).................................................................. 138

6.2.8

Refresh Timer/Counter (RTCNT)........................................................................ 141

6.2.9

Refresh Time Constant Register (RTCOR).......................................................... 141

6.3

Overview of Bus Control .................................................................................................. 142

6.3.1

Area Partitioning.................................................................................................. 142

6.3.2

Bus Specifications................................................................................................ 143

6.3.3

Memory Interfaces ............................................................................................... 144

6.3.4

Advanced Mode ................................................................................................... 145

6.3.5

Areas in Normal Mode......................................................................................... 146

6.3.6

Chip Select Signals .............................................................................................. 147

6.4

Basic Bus Interface ........................................................................................................... 148

6.4.1

Overview.............................................................................................................. 148

6.4.2

Data Size and Data Alignment ............................................................................. 148

6.4.3

Valid Strobes....................................................................................................... 150

6.4.4

Basic Timing........................................................................................................ 151

6.4.5

Wait Control ........................................................................................................ 159

6.5

DRAM Interface................................................................................................................ 161

6.5.1

Overview.............................................................................................................. 161

6.5.2

Setting DRAM Space........................................................................................... 161

6.5.3

Address Multiplexing........................................................................................... 162

6.5.4

Data Bus............................................................................................................... 162

6.5.5

Pins Used for DRAM Interface............................................................................ 163

6.5.6

Basic Timing........................................................................................................ 164

6.5.7

Precharge State Control ....................................................................................... 165

6.5.8

Wait Control ........................................................................................................ 166

6.5.9

Byte Access Control............................................................................................. 168

6.5.10 Burst Operation.................................................................................................... 169

6.5.11 Refresh Control.................................................................................................... 172

6.6

DMAC Single Address Mode and DRAM Interface......................................................... 176

6.6.1

When DDS = 1..................................................................................................... 176

6.6.2

When DDS = 0..................................................................................................... 177

6.7

Burst ROM Interface......................................................................................................... 178

6.7.1

Overview.............................................................................................................. 178

6.7.2

Basic Timing........................................................................................................ 178

6.7.3

Wait Control ........................................................................................................ 180

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