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HD6432351 датащи(PDF) 94 Page - Renesas Technology Corp

номер детали HD6432351
подробное описание детали  16-Bit Single-Chip Microcomputer
PDF  1025 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432351 датащи(HTML) 94 Page - Renesas Technology Corp

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Section 2 CPU
Rev. 3.00 Sep 15, 2006 page 60 of 988
REJ09B0330-0300
End of bus request
Bus request
Program execution
state
Bus-released state
Sleep mode
Exception-handling state
External interrupt
Software standby mode
RES = high
Reset state*1
STBY = high, RES = low
Hardware standby mode*2
Power-down state
Notes: 1.
2.
From any state except hardware standby mode, a transition to the reset state occurs whenever
RES
goes low. A transition can also be made to the reset state when the watchdog timer overflows.
From any state, a transition to hardware standby mode occurs when
STBY goes low.
SLEEP
instruction
with
SSBY = 0
SLEEP
instruction
with
SSBY = 1
Interrupt
request
End of bus
request
Bus
request
Request for
exception
handling
End of
exception
handling
Figure 2.15 State Transitions
2.8.2
Reset State
When the
RES input goes low all current processing stops and the CPU enters the reset state. The
CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the
NMI pin is low. All interrupts are masked in the reset state. Reset exception handling starts when
the
RES signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12,
Watchdog Timer (WDT).



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