HD6432351 datasheet(51/1025 Pages) RENESAS

51 / 1025 page

Section 1 Overview

Rev. 3.00 Sep 15, 2006 page 17 of 988

REJ09B0330-0300

Pin No.

Type

Symbol

TFP-120 FP-128

I/O

Name and Function

Bus control

CAS

116

126

Output Upper column address

strobe/column address strobe:

The 2CAS type DRAM upper column

address strobe signal.

LCAS

Output Lower column address strobe: The 2-

CAS type DRAM lower column

address strobe signal

WAIT

Input

Wait: Requests insertion of a wait

state in the bus cycle when

accessing external 3-state address

space.

DMA controller

(DMAC)

DREQ1,

DREQ0

62, 60

70, 66

Input

DMA request 1 and 0: These pins

request DMAC activation.

TEND1,

TEND0

63, 61

71, 69

Output DMA transfer end 1 and 0: These

pins indicate the end of DMAC data

transfer.

DACK1,

DACK0

111, 112 121, 122 Output DMA transfer acknowledge 1 and 0:

These are the DMAC single address

transfer acknowledge pins.

16-bit timer-

pulse unit

(TPU)

TCLKD to

TCLKA

105, 107,

109, 110

115, 117,

119, 120

Input

Clock input D to A: These pins input

an external clock.

TIOCA0,

TIOCB0,

TIOCC0,

TIOCD0

112 to

109

122 to

119

I/O

Input capture/ output compare match

A0 to D0: The TGR0A to TGR0D

input capture input or output

compare output, or PWM output pins.

TIOCA1,

TIOCB1

108, 107 118, 117 I/O

Input capture/ output compare match

A1 and B1: The TGR1A and TGR1B

input capture input or output

compare output, or PWM output pins.

TIOCA2,

TIOCB2

106, 105 116, 115 I/O

Input capture/ output compare match

A2 and B2: The TGR2A and TGR2B

input capture input or output

compare output, or PWM output pins.

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