HD6432351 datasheet(24/1025 Pages) RENESAS

24 / 1025 page

Rev. 3.00 Sep 15, 2006 page xxiv of xxxiv

7.5.1

Transfer Modes .................................................................................................... 233

7.5.2

Sequential Mode .................................................................................................. 236

7.5.3

Idle Mode............................................................................................................. 239

7.5.4

Repeat Mode ........................................................................................................ 242

7.5.5

Single Address Mode ........................................................................................... 246

7.5.6

Normal Mode....................................................................................................... 249

7.5.7

Block Transfer Mode ........................................................................................... 252

7.5.8

DMAC Activation Sources .................................................................................. 259

7.5.9

Basic DMAC Bus Cycles..................................................................................... 263

7.5.10 DMAC Bus Cycles (Dual Address Mode) ........................................................... 264

7.5.11 DMAC Bus Cycles (Single Address Mode)......................................................... 272

7.5.12 Write Data Buffer Function ................................................................................. 278

7.5.13 DMAC Multi-Channel Operation ........................................................................ 279

7.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC,

and the DMAC..................................................................................................... 280

7.5.15 NMI Interrupts and DMAC.................................................................................. 281

7.5.16 Forced Termination of DMAC Operation............................................................ 282

7.5.17 Clearing Full Address Mode ................................................................................ 283

7.6

Interrupts ........................................................................................................................... 284

7.7

Usage Notes ...................................................................................................................... 285

Section 8 Data Transfer Controller (DTC)................................................................... 291

8.1

Overview........................................................................................................................... 291

8.1.1

Features................................................................................................................ 291

8.1.2

Block Diagram ..................................................................................................... 292

8.1.3

8.2

Register Descriptions ........................................................................................................ 294

8.2.1

DTC Mode Register A (MRA) ............................................................................ 294

8.2.2

DTC Mode Register B (MRB)............................................................................. 296

8.2.3

DTC Source Address Register (SAR) .................................................................. 297

8.2.4

DTC Destination Address Register (DAR) .......................................................... 297

8.2.5

DTC Transfer Count Register A (CRA)............................................................... 298

8.2.6

DTC Transfer Count Register B (CRB)............................................................... 298

8.2.7

DTC Enable Registers (DTCER) ......................................................................... 299

8.2.8

DTC Vector Register (DTVECR)........................................................................ 300

8.2.9

Module Stop Control Register (MSTPCR) .......................................................... 301

8.3

Operation........................................................................................................................... 302

8.3.1

Overview.............................................................................................................. 302

8.3.2

Activation Sources ............................................................................................... 304

8.3.3

DTC Vector Table ............................................................................................... 305

8.3.4

Location of Register Information in Address Space............................................. 308

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