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HD6432351 датащи(PDF) 166 Page - Renesas Technology Corp |
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HD6432351 датащи(HTML) 166 Page - Renesas Technology Corp |
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166 / 1025 page ![]() Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 132 of 988 REJ09B0330-0300 6.2.4 Bus Control Register H (BCRH) 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 BRSTRM 0 R/W 4 BRSTS1 1 R/W 3 BRSTS0 0 R/W 0 RMTS0 0 R/W 2 RMTS2 0 R/W 1 RMTS1 0 R/W Bit Initial value R/W : : : BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 Description 0 Idle cycle not inserted in case of successive external read cycles in different areas 1 Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6—Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed. Bit 6 ICIS0 Description 0 Idle cycle not inserted in case of successive external read and external write cycles 1 Idle cycle inserted in case of successive external read and external write cycles (Initial value) Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. In normal mode, the selection can be made from the entire external space. Bit 5 BRSTRM Description 0 Area 0 is basic bus interface (Initial value) 1 Area 0 is burst ROM interface |
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