38K2 datasheet(32/358 Pages) RENESAS

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FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 13 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

I/O PORTS

The I/O ports have direction registers which determine the input/

output direction of each individual pin. Each bit in a direction reg-

ister corresponds to one pin, and each pin can be set to be input

port or output port.

When “0” is written to the bit corresponding to a pin, that pin be-

comes an input pin. When “1” is written to that bit, that pin be-

comes an output pin.

If data is read from a pin set to output, the value of the port output

latch is read, not the value of the pin itself. Pins set to input are

floating. If a pin set to input is written to, only the port output latch

is written to and the pin remains floating.

Table 5 I/O ports functions

Related SFRs

Port P0 pull-up control

AD control register

EXB control register

Serial I/O control

EXB control register

Serial I/O control

EXB control register

Serial I/O control

EXB control register

Serial I/O control

EXB control register

Port P5 pull-up control

Interrupt edge selection

Timer X mode register

Input/Output

Input/output,

individual bits

Name

Port P0

Port P1

Port P2

Port P3

Port P4

Port P5

Port P6

P00–P07

P10–P17

P24–P27

P30–P32

P33/ExINT

P34/ExCS

P35/ExWR

P36/ExRD

P37/ExA0

P40/RxD/

ExDREQ

P41/TxD/

ExDACK

P42/SCLK/

ExTC

P43/SRDY/

ExA1

P50/INT0

P52/INT1

P51/CNTR0

P53–P57

P60–P63

Non-Port Function

Key-on wake up

A/D conversion input

External bus interface

funciton I/O

External bus interface

funciton output

External bus interface

funciton input

Serial I/O input

External bus interface

funciton output

Serial I/O output

External bus interface

funciton input

Serial I/O I/O

External bus interface

funciton input

Serial I/O output

External bus interface

funciton input

External interrupt input

Timer X function I/O

I/O Format

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

(Power source is

VCCE)

CMOS compatible

input level

CMOS 3-state output

CMOS compatible

input level

CMOS 3-state output

(Power source is

VccE)

CMOS compatible

input level

CMOS 3-state output

Diagram No.

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

Note: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate poten-

tial, a current will flow from VCC to VSS through the input-stage gate.

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