38K2 datasheet(99/358 Pages) RENESAS

99 / 358 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 80 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

Fig. 116 Index01[low]; Structure of Transmit/Receive buffer register

Fig. 117 Index02[low]; Structure of Memory channel operation mode register

Fig. 118 Index03[low]; Structure of Memory address counter

–

RXBUF/

TXBUF

–

Index =0116 : Transmit/Receive buffer register (RXBUF/TXBUF) [address 003416]

Bit name

Bit symbol

At reset

Function

H/W

S/W

The data received from an external bus is written here

at the rise timing of external write signal.

The data transmitted to an external bus is written here

at the timing of internal CPU write or memory write.

The receive buffer register (RXBUF) contents can be read out by reading to this address with the CPU. The data which the

CPU has written to this address is stored in the transmit buffer register (TXBUF).

However, do not perform write operation with the CPU to this address if the memory channel direction control bits of

memory channel operation mode register is “102” (transmit mode) and the memory channel status bits of EXB interrupt

source register are “012” or “102” (memory channel being operating).

MC_DIR

[1:0]

BURST

b7:b3

–

Index =0216 : Memory channel operation mode register (MCHMOD) [address 003416]

00000

Bit name

Bit symbol

At reset

Function

H/W

S/W

b1b0

0 0 : Operation disabled

0 1 : Receive mode

1 0 : Transmit mode

1 1 : Do not set.

0 : Cycle mode (each byte transfer according to

assertion or negation)

1 : Burst mode (continuous transfer till the terminal

count)

Write “0” when writing.

“0” is read when reading.

–: State remaining

Memory channel direction

control bit

Burst bit

Not used

IM_A

[7:0]

–

Index = 0316 : Memory address counter (MEMADL) [address 003416]

Bit name

Bit symbol

At reset

Function

H/W

S/W

–

channel operation beginning.

This contents are increased each time one memory

access ends.

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