38K2 datasheet(16/358 Pages) RENESAS

16 / 358 page

Rev.2.00

Oct 15, 2006

page 12 of 14

38K2 Group

REJ09B0338-0200

Fig. 3.4.80 Structure of AD conversion register 2 ..................................................................... 71

Fig. 3.4.81 Structure of Watchdog timer control register .......................................................... 72

Fig. 3.4.82 Structure of CPU mode register ............................................................................... 72

Fig. 3.4.83 Structure of Interrupt request register 1 .................................................................. 73

Fig. 3.4.84 Structure of Interrupt request register 2 .................................................................. 73

Fig. 3.4.85 Structure of Interrupt control register 1 ................................................................... 74

Fig. 3.4.86 Structure of Interrupt control register 2 ................................................................... 74

Fig. 3.4.87 Structure of Serial I/O control register ..................................................................... 75

Fig. 3.4.88 Structure of UART control register ........................................................................... 75

Fig. 3.4.89 Structure of Baud rate generator .............................................................................. 76

Fig. 3.4.90 Structure of EP01 MAX. packet size register ......................................................... 76

Fig. 3.4.91 Structure of EP02 MAX. packet size register ......................................................... 76

Fig. 3.4.92 Structure of EP03 MAX. packet size register ......................................................... 77

Fig. 3.4.93 Structure of EP00 buffer area set register .............................................................. 77

Fig. 3.4.94 Structure of EP01 buffer area set register .............................................................. 77

Fig. 3.4.95 Structure of EP02 buffer area set register .............................................................. 78

Fig. 3.4.96 Structure of EP03 buffer area set register .............................................................. 78

Fig. 3.4.97 Structure of EP10 buffer area set register .............................................................. 78

Fig. 3.4.98 Structure of EP11 buffer area set register .............................................................. 79

Fig. 3.4.99 Structure of Port P0 pull-up control register ........................................................... 79

Fig. 3.4.100 Structure of Port P5 pull-up control register ......................................................... 80

Fig. 3.4.101 Structure of Interrupt edge selection register ....................................................... 80

Fig. 3.4.102 Structure of PLL control register ............................................................................ 81

Fig. 3.4.103 Structure of Downstream port control register ...................................................... 81

Fig. 3.4.104 Structure of MISRG .................................................................................................. 82

Fig. 3.4.105 Structure of Flash memory control register ........................................................... 82

List of figures

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