38K2 datasheet(15/358 Pages) RENESAS

15 / 358 page

Rev.2.00

Oct 15, 2006

page 11 of 14

38K2 Group

REJ09B0338-0200

List of figures

Fig. 3.4.27 Structure of EP03 control register 2 ........................................................................ 48

Fig. 3.4.28 Structure of EP10 control register 2 ........................................................................ 49

Fig. 3.4.29 Structure of EP11 control register 2 ........................................................................ 49

Fig. 3.4.30 Structure of EP00 control register 3 ........................................................................ 49

Fig. 3.4.31 Structure of EP01 control register 3 ........................................................................ 50

Fig. 3.4.32 Structure of EP02 control register 3 ........................................................................ 50

Fig. 3.4.33 Structure of EP03 control register 3 ........................................................................ 50

Fig. 3.4.34 Structure of EP10 control register 3 ........................................................................ 51

Fig. 3.4.35 Structure of EP00 interrupt source register ............................................................ 51

Fig. 3.4.36 Structure of EP01 interrupt source register ............................................................ 52

Fig. 3.4.37 Structure of EP02 interrupt source register ............................................................ 52

Fig. 3.4.38 Structure of EP03 interrupt source register ............................................................ 53

Fig. 3.4.39 Structure of EP10 interrupt source register ............................................................ 54

Fig. 3.4.40 Structure of EP11 interrupt source register ............................................................ 54

Fig. 3.4.41 Structure of EP00 byte number register .................................................................. 55

Fig. 3.4.42 Structure of EP01 byte number register 0 .............................................................. 55

Fig. 3.4.43 Structure of EP02 byte number register 0 .............................................................. 55

Fig. 3.4.44 Structure of EP03 byte number register 0 .............................................................. 56

Fig. 3.4.45 Structure of EP10 byte number register .................................................................. 56

Fig. 3.4.46 Structure of EP11 byte number register 0 .............................................................. 56

Fig. 3.4.47 Structure of EP01 byte number register 1 .............................................................. 57

Fig. 3.4.48 Structure of EP02 byte number register 1 .............................................................. 57

Fig. 3.4.49 Structure of EP03 byte number register 1 .............................................................. 57

Fig. 3.4.50 Structure of Prescaler12, Prescaler X ..................................................................... 58

Fig. 3.4.51 Structure of Timer 1 ................................................................................................... 58

Fig. 3.4.52 Structure of Timer 2, Timer X ................................................................................... 59

Fig. 3.4.53 Structure of Timer X mode register ......................................................................... 59

Fig. 3.4.54 Structure of Transmit/Receive buffer register ......................................................... 60

Fig. 3.4.55 Structure of Serial I/O status register ...................................................................... 60

Fig. 3.4.56 Structure of HUB interrupt source enable register ................................................. 61

Fig. 3.4.57 Structure of HUB interrupt source register .............................................................. 61

Fig. 3.4.58 Structure of HUB downstream port index register ................................................. 61

Fig. 3.4.59 Structure of DP1 interrupt source register .............................................................. 62

Fig. 3.4.60 Structure of DP2 interrupt source register .............................................................. 63

Fig. 3.4.61 Structure of DP1 control register .............................................................................. 64

Fig. 3.4.62 Structure of DP2 control register .............................................................................. 64

Fig. 3.4.63 Structure of DP1 status register ............................................................................... 65

Fig. 3.4.64 Structure of DP2 status register ............................................................................... 65

Fig. 3.4.65 Structure of EXB interrupt source enable register ................................................. 65

Fig. 3.4.66 Structure of EXB interrupt source register .............................................................. 66

Fig. 3.4.67 Structure of EXB index register ................................................................................ 66

Fig. 3.4.68 Structure of Register window 1 ................................................................................. 67

Fig. 3.4.69 Index00[low]; Structure of External I/O configuration register ............................ 67

Fig. 3.4.70 Index01[low]; Structure of Transmit/Receive buffer register ................................. 68

Fig. 3.4.71 Index02[low]; Structure of Memory channel operation mode register ................. 68

Fig. 3.4.72 Index03[low]; Structure of Memory address counter .............................................. 68

Fig. 3.4.73 Index04[low]; Structure of End address register .................................................... 69

Fig. 3.4.74 Structure of Register window 2 ................................................................................. 69

Fig. 3.4.75 Index00[high]; Structure of External I/O configuration register ........................... 69

Fig. 3.4.76 Index03[high]; Structure of Memory address counter ............................................ 70

Fig. 3.4.77 Index04[high]; Structure of End address register ................................................... 70

Fig. 3.4.78 Structure of AD control register ................................................................................ 70

Fig. 3.4.79 Structure of AD conversion register 1 ..................................................................... 71

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