38K2 datasheet(49/358 Pages) RENESAS

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FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 30 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

USB Interrupt Function

USB Interrupt Control Circuit (USBINTCON) has 3 requests and

22 USB-device interrupt request sources. Each interrupt source

occurred.

Table 7 shows the list of USB interrupt sources.

Table 7 USB interrupt sources

Interrupt request bit

(IREQ1: Address 003C16)

USB bus reset

USB interrupt bit

(USBIREQ: Address 001716)

—

Interrupt source

At USB bus reset signal detection:

After enabling the USB module (USBE = “1”), an interrupt request occurs

when 2.5

µs SE0 state is detected in D0+/D0- port.

(Equivalent to 120-clock length when fUSB = 48 MHz)

At SOF packet receive:

After enabling the USB module (USBE = “1”), an interrupt request occurs

when SOF packet is detected in D0+/D0- port.

Its occurrence does not depend on frame-time or CRC value after SOF

packet is transferred.

(Normally, SOF packet detection occurs only when fUSB = 48 MHz)

At Endpoint 00 data transfer complete:

•Buffer ready (read/write enabled state)

•Control transfer completed

•Status stage transition

•SETUP buffer ready (read enabled state)

•Control transfer error

At Endpoint 01 data transfer complete:

•Buffer 0 ready (read/write enabled state)

•Buffer 1 ready (read/write enabled state)

•Transfer error

At Endpoint 02 data transfer complete:

•Buffer 0 ready (read/write enabled state)

•Buffer 1 ready (read/write enabled state)

•Transfer error

At Endpoint 03 data transfer complete:

•Buffer 0 ready (read/write enabled state)

•Buffer 1 ready (read/write enabled state)

•Transfer error

At Endpoint 10 data transfer complete:

•Buffer ready (read/write enabled state)

•Control transfer completed

•Status stage transition

•SETUP buffer ready (read enabled state)

•Control transfer error

At Endpoin 11 data transfer complete:

•Buffer 0 ready (write enabled state)

At suspend signal detection:

After enabling the USB module (USBE = “1”), an interrupt request occurs

when 3 ms J state is detected in D0+/D0- port.

(Equivalent to 144,000 clock-length when fUSB = 48MHz)

At resume signal detection:

After enabling the USB module (USBE = “1”) and resume interrupt (RSME

= “1”), an interrupt request occurs when a bus state change (J state to

SE0 or K state) is detected in D0- port.

USB SOF

—

USB device

EP00

EP01

EP02

EP03

EP10

EP11

SUS

RSM

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