38K2 datasheet(10/358 Pages) RENESAS

10 / 358 page

Rev.2.00

Oct 15, 2006

page 6 of 14

38K2 Group

REJ09B0338-0200

List of figures

Fig. 96 Structure of DP1 interrupt source register ................................................................... 65

Fig. 97 Structure of DP1 control register ................................................................................... 66

Fig. 98 Structure of DP1 status register .................................................................................... 66

Fig. 99 Structure of DP2 interrupt source register ................................................................... 67

Fig. 100 Structure of DP2 control register ................................................................................. 68

Fig. 101 Structure of DP2 status register .................................................................................. 68

Fig. 102 Structure of Downstream port control register .......................................................... 69

Fig. 103 External bus interface ................................................................................................... 70

Fig. 104 Data transfer timing of memory channel .................................................................... 70

Fig. 105 External bus interface (EXB) pin assignment ............................................................ 71

Fig. 106 Block diagram of external bus interface (EXB) ......................................................... 72

Fig. 107 EXB related registers (1) .............................................................................................. 76

Fig. 108 EXB related registers (2) .............................................................................................. 76

Fig. 109 Structure of EXB interrupt source enable register .................................................... 77

Fig. 110 Structure of EXB interrupt source register ................................................................. 77

Fig. 111 Structure of EXB index register ................................................................................... 78

Fig. 112 Structure of Register window 1 ................................................................................... 78

Fig. 113 Structure of Register window 2 ................................................................................... 78

Fig. 114 Index00[low]; Structure of External I/O configuration register ................................. 79

Fig. 115 Index00[high]; Structure of External I/O configuration register .............................. 79

Fig. 116 Index01[low]; Structure of Transmit/Receive buffer register .................................... 80

Fig. 117 Index02[low]; Structure of Memory channel operation mode register .................... 80

Fig. 118 Index03[low]; Structure of Memory address counter ................................................ 80

Fig. 119 Index03[high]; Structure of Memory address counter ............................................... 81

Fig. 120 Index04[low]; Structure of End address register ....................................................... 81

Fig. 121 Index04[high]; Structure of End address register ...................................................... 81

Fig. 122 CPU channel receiving operation ................................................................................ 82

Fig. 123 CPU channel tranmitting operation ............................................................................. 83

Fig. 124 Memory channel receiving operation (1) .................................................................... 84

Fig. 125 Memory channel receiving operation (2) .................................................................... 85

Fig. 126 Memory channel receiving operation (3) .................................................................... 86

Fig. 127 Memory channel tranmitting operation (1) ................................................................. 87

Fig. 128 Memory channel tranmitting operation (2) ................................................................. 88

Fig. 129 Multichannel RAM timing diagram (no wait) .............................................................. 89

Fig. 130 Multichannel RAM timing diagram (one wait) ............................................................ 89

Fig. 131 Multichannel RAM operation example ......................................................................... 90

Fig. 132 Structure of AD control register ................................................................................... 91

Fig. 133 10-bit A/D mode reading .............................................................................................. 91

Fig. 134 A/D converter block diagram ........................................................................................ 92

Fig. 135 Block diagram of Watchdog timer ............................................................................... 93

Fig. 136 Structure of Watchdog timer control register ............................................................. 93

Fig. 137 Example of reset circuit ................................................................................................ 94

Fig. 138 Reset sequence ............................................................................................................. 94

Fig. 139 Block diagram of PLL circuit ........................................................................................ 95

Fig. 140 Structure of PLL control register ................................................................................. 96

Fig. 141 Ceramic resonator or quartz-crystal oscilltor circuit ................................................. 98

Fig. 142 External clock input circuit ........................................................................................... 98

Fig. 143 Structure of MISRG ....................................................................................................... 98

Fig. 144 System clock generating circuit block diagram (single-chip mode) ........................ 98

Fig. 145 State transitions of clock .............................................................................................. 99

Fig. 146 Block diagram of built-in flash memory .................................................................... 101

Fig. 147 Structure of flash memory control register ............................................................... 102

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