38K2 datasheet(68/358 Pages) RENESAS

68 / 358 page

FUNCTIONAL DESCRIPTION

Rev.2.00

Oct 15, 2006

page 49 of 130

38K2 Group

REJ09B0338-0200

HARDWARE

(4) Endpoint 03

Fig. 65 Structure of EP03 set register

Fig. 66 Structure of EP03 control register 1

Double buffer beginning address set

bit

Buffer mode select bit

Sequence toggle bit clear bit

Interrupt toggle mode select bit

Transfer direction bit

Transfer type bit

BSIZ03

[1:0]

DBLB03

SQCL03

ITMD03

DIR03

TYP03

[1:0]

–

EP03 set register (EP03CFG) [address 001916]

Bit name

Bit symbol

At reset

Function

H/W

S/W

In double buffer mode set the beginning address of buffer 1

area, using a relative value for the beginning address of

buffer 0.

b1b0

0 0 = 8 bytes

0 1 = 16 bytes

1 0 = 64 bytes

1 1 = 128 bytes

0 : Single buffer mode

1 : Double buffer mode

0 : Toggle bit clear disabled

1 : Writing “1” clears the toggle bit and DATA0 is used

as the next data PID.

“0” is always read when reading.

0 : Normal mode

1 : Continuous toggle mode (valid at Interrupt IN transfer)

0 : OUT (Data is received from the host.)

1 : IN (Data is transmitted to the host.)

b7b6

0 0 : Transfer disabled

0 1 : Bulk transfer

1 0 : Interrupt transfer

1 1 : Isochronous transfer

–: State remaining

Response PID bit

Not used

PID03

[1:0]

b7:b2

–

EP03 control register 1 (EP03CON1) [address 001A16]

Bit name

Bit symbol

At reset

Function

H/W

S/W

b1 b0

0 0 : NAK

0 1 : Automatic response (ACK, NAK, DATA0, DATA1)

1 X : STALL

At occurrence of over-max. packet size :

B1 is set to “1” by the hardware.

Write “0” when writing.

“0” is read when reading.

–: State remaining

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