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M16C/29 датащи(PDF) 304 Page - Renesas Technology Corp |
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M16C/29 датащи(HTML) 304 Page - Renesas Technology Corp |
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304 / 499 page ![]() 16. MULTI-MASTER I2C bus INTERFACE p u o r G 9 2 / C 6 1 M page 280 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R Figure 16.16 Start condition generation timing diagram Figure 16.17 Stop condition generation timing diagram Table 16.8 Start/Stop generation timing table As mentioned above, when bits MST and TRX are set to 1, START condition or STOP condition mode is entered by writing 1 or 0 to the BB flag in the S10 register and writing 0 to the PIN bit and 4 low-order bits in the S10 register at the same time. Then SDAMM is left open in the START condition standby mode and SDAMM is set to low-level ("L") in the STOP condition standby mode. When the S00 register is set, the START/STOP conditions are generated. In order to set bits MST and TRX to 1 without generating the START/STOP conditions, write 1 to the 4 low-order bits simultaneously. Table 16.9 lists functions along with the S10 register settings. N OTE: 1. Actual time at the time of VIIC = 4MHz, The contents in () denote cycle numbers. Table 16.9 S10 Register Settings and Functions S00 register SCL SDA Hold time Setup time S00 register SCL SDA Setup time Hold time n o it i d n o C p o t S /t r a t S ti B t c e l e S n o it a r e n e G e d o M k c o l C d r a d n a t Se d o M k c o l C d e e p s - h g i H e m it p u t e S 00 . 5 µ ) s e l c y c 0 2 ( s5 . 2 µ ) s e l c y c 0 1 ( s 10 . 3 1 µ ) s e l c y c 2 5 ( s5 . 6 µ ) s e l c y c 6 2 ( s e m it d l o H 00 . 5 µ ) s e l c y c 0 2 ( s5 . 2 µ ) s e l c y c 0 1 ( s 10 . 3 1 µ ) s e l c y c 2 5 ( s5 . 6 µ ) s e l c y c 6 2 ( s s g n it t e S r e t s i g e R 0 1 S n o it c n u F T S MX R TB BN I PL AS A A0 S AB R L 1 1 1 000 0 0 r e t s a m n i y b d n a t s n o it i d n o c T R A T S e h t p u g n it t e S e d o m ti m s n a rt 1 1 0 000 0 0 r e t s a m n i y b d n a t s n o it i d n o c P O T S e h t p u g n it t e S e d o m ti m s n a rt 1 / 01 / 0- 0 1 1 1 1 o t r e f e r ( e d o m n o it a c i n u m m o c h c a e p u g n it t e S 5 . 6 1 I2 r e t s i g e r s u t a t s C ) |
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