M16CSLASH29 datasheet(301/499 Pages) RENESAS

301 / 499 page

16. MULTI-MASTER I2C bus INTERFACE

page 277

16.8 I2C0 START/STOP Condition Control Register (S2D0 Register)

The S2D0 register controls the START/STOP condition detections.

16.8.1 Bit0-Bit4: START/STOP Condition Setting Bits (SSC0-SSC4)

The SCL release time and the set-up and hold times are mesured on the base of the I2C bus system clock

(VIIC). Therefore, the detection conditions changes, depending on the oscillation frequency (XIN) and the

I2C bus system clock select bits. It is necessary to set bits SSC4 to SSC0 to the appropriate value to set

the SCL release time, the set-up and hold times by the system clock frequency (See Table 16.10). Do

not set odd numbers or 000002 to bits SSC4 to SSC0. Table 16.2 shows the reference value to bits

SSC4 to SSC0 at each oscillation frequency in standard clock mode. The detection of START/STOP

conditions starts immediately after the ES0 bit in the S1D0 register is set to 1 (I2C bus interface enabled).

16.8.2 Bit5: SCL/SDA Interrupt Pin Polarity Select Bit (SIP)

The The SIP bit detect the rising edge or the falling edge of the SCLMM or SDAMM to generate SCL/SDA

interrupts. The SIP bit selects the polarity of the SCLMM or the SDAMM for interrupt.

16.8.3 Bit6 : SCL/SDA Interrupt Pin Select Bit (SIS)

The SIS bit selects a pin to enable SCL/SDA interrupt.

NOTE:

1. The SCL/SDA interrupt request may be set when changing the SIP, SIS and ES0 bit settings in the

S1D0 register. When using the SCL/SDA interrupt, set the above bits, while the SCL/SDA interrupt

is disabled. Then, enable the SCL/SDA interrupt after setting the SCL/SDA bit in the IR register to 0.

16.8.4 Bit7: START/STOP Condition Generation Select Bit (STSPSEL)

The STSPSEL bit selects the set-up/hold times, based on the I2C system clock cycles, when the START/

STOP condition is generated (See Table 16.8). Set the STSPSEL bit to 1 if the I2C bus system clock

frequency is over 4MHz.

M16C/29 датащи(PDF) 301 Page - Renesas Technology Corp