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M16C/29 датащи(PDF) 302 Page - Renesas Technology Corp |
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M16C/29 датащи(HTML) 302 Page - Renesas Technology Corp |
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302 / 499 page ![]() 16. MULTI-MASTER I2C bus INTERFACE p u o r G 9 2 / C 6 1 M page 278 8 5 4 f o 7 0 0 2 , 0 3 .r a M 2 1 . 1 . v e R 2 1 1 0 - 1 0 1 0 B 9 0 J E R 16.9 START Condition Generation Method Set the MST bit, TRX bit and BB flags in the S10 register to 1 and set the PIN bit and 4 low-order bits in the S10 register to 0 simultaneously, to enter START condition standby mode, when the ES0 bit in the S1D0 register is set to 1 (I2C bus interface enabled) and the BB flag is set to 0 (bus free). When the slave address is written to the S00 register next, START condition is generated and the bit counter is reset to 0002 and 1- byte SCL signal is output. The START condition generation timing varies between standard clock mode and high-speed clock mode. See Figure 16.16 and Table 16.8. Figure 16.14 Start condition generation flow chart Interrupt disable BB=0? S10 = E016 S00 = Data Interrupt enable No Yes Start condition trigger generation Start condition standby status setting *Data = Slave address data |
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