M16CSLASH29 datasheet(113/499 Pages) RENESAS

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10. Watchdog Timer

page 89

Figure 10.1 Watchdog Timer Block Diagram

10. Watchdog Timer

The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend

using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which

counts down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a watchdog

timer interrupt request or apply a watchdog timer reset as an operation to be performed when the watchdog timer

underflows after reaching the terminal count can be selected using the PM12 bit in the PM1 register. The PM12

bit can only be set to 1 (reset). Once this bit is set to 1, it cannot be set to 0 (watchdog timer interrupt) in a

program. Refer to 5.3 Watchdog Timer Reset for the details of watchdog timer reset.

When the main clock source is selected for CPU clock, on-chip oscillator clock, PLL clock, the WDC7 bit in the

WDC register value for prescaler can be chosen to be 16 or 128. If a sub-clock is selected for CPU clock, the

prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be calculated as

given below. The period of watchdog timer is, however, subject to an error due to the prescaler.

For example, when CPU clock is set to 16 MHz and the divide-by-N value for the prescale ris set to 16, the

watchdog timer period is approx. 32.8 ms.

The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that

the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start

counting by writing to the WDTS register.

Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the

beginning of the watchdog timer interrupt routine.

In stop mode and wait mode, the watchdog timer and prescaler are stopped. Counting is resumed from the held

value when the modes or state are released.

Figure 10.1

shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related

registers.

With main clock source chosen for CPU clock, on-chip oscillator clock, PLL clock

Watchdog timer period =

With sub-clock chosen for CPU clock

Prescaler dividing (2) X Watchdog timer count (32768)

CPU clock

Watchdog timer period =

Prescaler dividing (16 or 128) X Watchdog timer count (32768)

CPU clock

Write to WDTS register

PM12 = 0

Watchdog timer

Set to 7FFF16

1/128

1/16

CM07 = 0

WDC7 = 1

CM07 = 0

WDC7 = 0

CM07 = 1

1/2

Prescaler

PM12 = 1

Reset

PM22 = 0

PM22 = 1

On-chip oscillator clock

Internal reset signal

(low active)

Watchdog timer

interrupt request

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