M16CSLASH29 datasheet(116/499 Pages) RENESAS

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11. DMAC

page 92

Item

Specification

No. of channels

2 (cycle steal method)

Transfer memory space

• From any address in the 1M bytes space to a fixed address

• From a fixed address to any address in the 1M bytes space

• From a fixed address to a fixed address

Maximum No. of bytes transferred 128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)

DMA request factors (1, 2)

________

Falling edge of INT0 or INT1

________

Both edge of INT0 or INT1

Timer A0 to timer A4 interrupt requests

Timer B0 to timer B2 interrupt requests

UART0 transfer, UART0 reception interrupt requests

UART1 transfer, UART1 reception interrupt requests

UART2 transfer, UART2 reception interrupt requests

SI/O3, SI/O4 interrupt requests

A/D conversion interrupt requests

Timer S(IC/OC) requests

Software triggers

Channel priority

DMA0 > DMA1 (DMA0 takes precedence)

Transfer unit

8 bits or 16 bits

Transfer address direction

forward or fixed (The source and destination addresses cannot both be

in the forward direction)

Transfer mode Single transfer Transfer is completed when the DMAi transfer counter (i = 0,1)

underflows after reaching the terminal count

Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value

of the DMAi transfer counter reload register and a DMA transfer is con

tinued with it

DMA interrupt request generation timing When the DMAi transfer counter underflowed

DMA startup

Data transfer is initiated each time a DMA request is generated when

the

DMAE bit in the DMAiCON register = 1 (enabled)

DMA shutdown Single transfer

• When the DMAE bit is set to 0 (disabled)

• After the DMAi transfer counter underflows

Repeat transfer When the DMAE bit is set to 0 (disabled)

When a data transfer is started after setting the DMAE bit to 1 (en

abled), the forward address pointer is reloaded with the value of the

SARi or the DARi pointer whichever is specified to be in the forward

direction and the DMAi transfer counter is reloaded with the value of the

DMAi transfer counter reload register

Table 11.1 DMAC Specifications

NOTES:

1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the

interrupt control register.

2. The selectable causes of DMA requests differ with each channel.

3. Make sure that no DMAC-related registers (addresses 002016 to 003F16) are accessed by the DMAC.

Reload timing for forward ad-

dress pointer and transfer

counter

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