M16CSLASH29 datasheet(115/499 Pages) RENESAS

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11. DMAC

page 91

11. DMAC

Note

Do not use SI/O4 interrupt request as a DMA request in the 64-pin package.

The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.

Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit)

data from the source address to the destination address. The DMAC uses the same data bus as used by

the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of

a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time

after a DMA request is generated. Figure 11.1 shows the block diagram of the DMAC. Table 11.1 shows

the DMAC specifications. Figures 11.2 to 11.4 show the DMAC-related registers.

Figure 11.1 DMAC Block Diagram

A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0,1), as well as by an

interrupt request which is generated by any function specified by the DMS and bits DSEL3 to DSEL0 in the

DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I

flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt

request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not

affect interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer.

A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON

the DMA transfer cycle, the number of transfer requests generated and the number of times data is trans-

ferred may not match. For details, refer to “DMA Requests”.

Data bus low-order bits

DMA latch high-order bits

DMA latch low-order bits

DMA0 source pointer SAR0(20)

DMA0 destination pointer DAR0 (20)

DMA0 forward address pointer (20) (1)

Data bus high-order bits

Address bus

DMA1 destination pointer DAR1 (20)

DMA1 source pointer SAR1 (20)

DMA1 forward address pointer (20) (1)

DMA0 transfer counter reload register TCR0 (16)

DMA0 transfer counter TCR0 (16)

DMA1 transfer counter reload register TCR1 (16)

DMA1 transfer counter TCR1 (16)

(addresses 0029 16, 002816)

(addresses 0039 16, 003816)

(addresses 002216 to 002016)

(addresses 002616 to 002416)

(addresses 003216 to 003016)

(addresses 003616 to 003416)

NOTE:

1. Pointer is incremented by a DMA request.

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